This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2001-75934 filed on Mar. 16th, 2001; the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to digital circuits, and more particularly relates to a multiplied clock generating circuit for generating and outputting a times-M clock signal that has a higher frequency than an arbitrary input clock by a factor M.
2. Description of the Related Art
FIG. 1 is a schematic diagram showing an example of a multiplied clock generating circuit for generating a feedback clock signal fd by dividing an output clock signal fo by M and controlling the frequency and the phase of the feedback clock signal fd to match those of an input clock signal fr. In the figure, the multiplied clock generating circuit is composed of a frequency divider circuit 101, a phase comparator circuit 102, a frequency comparator circuit 103, a clock phase synchronization circuit 104, an oscillator control circuit 105 and an oscillator circuit 106.
The frequency divider circuit 101 serves to generate the feedback clock signal fd by dividing by M the output clock signal fo while the phase comparator circuit 102 serves to detect the phase difference between the input clock signal fr and the feedback clock signal fd and output the result of detection to the frequency comparator circuit 103 and the clock phase synchronization circuit 104. The frequency comparator circuit 103 and the clock phase synchronization circuit 104 serve to calculate how much the output clock signal fo should be modified for adjusting the frequency and the phase of the feedback clock signal fd to the input clock signal fr on the basis of information given by the phase comparator circuit 102, and outputting the results to the oscillator control circuit 105. The oscillator control circuit 105 takes control of the oscillator circuit 106 to modify the output clock signal fo on the basis of the information as given from the frequency comparator circuit 103 and the clock phase synchronization circuit 104.
FIG. 2 is a schematic diagram showing an example of the configuration of the oscillator circuit 106. In the figure, the oscillator circuit 106 is composed of a fixed-delay-time delay circuit 111, a variable-delay-time delay circuit 112 and an oscillation control circuit 113. The variable-delay-time delay circuit 112 is composed of four variable-delay-time delay cells (dcell) 114. The delay time of each variable-delay-time delay cell 114 is (d+xcex94d) when the signal dlysw*(*=0 to 3) is set to a low level and is d when the signal dlysw*(*=0 to 3) is set to a high level. When a signal osc_act is low, the output clock signal fo is fixed to a low level by the oscillation control circuit 113 so that the oscillation of the oscillator circuit is halted. Accordingly, the oscillator control circuit 105 receives the information from the frequency comparator circuit 103 and the clock phase synchronization circuit 104 and takes control of the variable-delay-time delay cell 114 in order to modify the delay time thereof.
For example, if the input signals to the variable-delay-time delay cells 114 are fixed dlysw3=dlysw2=low and dlysw1=dlysw0=high so that the feedback clock signal fd has a frequency xcfx841 lower than that of the input clock signal fr while the input signals to the variable-delay-time delay cells 114 are fixed dlysw3=low and dlysw1=dlysw0=dlysw2=high so that the feedback clock signal fd has a frequency xcfx842 higher than that of the input clock signal fr, then the input signals to the variable-delay-time delay cells 114 are fixed such that dlysw3=low and dlysw1=dlysw0=high while the signal dlysw2 is controlled by maintaining or inverting it for each cycle of the feedback clock signal fd in order to the clock period of the feedback clock signal fd is either xcfx841 or xcfx842 as illustrated in the timing chart of FIG. 3.
FIG. 3 is a timing chart in which the phase of the feedback clock signal fd is adjusted in order that the rising edge of the feedback clock signal fd coincides with the rising edge of the input clock signal fr. Since the rising edge edge0 of the feedback clock signal fd is advanced ahead of the rising edge of the input clock signal fr, the clock period of the feedback clock signal fd starting from the rising edge edge0 is set to xcfx841 which is longer than the clock period of the input clock signal fr. On the other hand, since the rising edge edge1 lags behind the rising edge of the input clock signal fr, the clock period of the feedback clock signal fd starting from the rising edge edge1 is then set to xcfx842, which is shorter than the clock period of the input clock signal fr and maintained until the rising edge edge4 appears from which the rising edge of the feedback clock signal fd is advanced again ahead of the rising edge of the input clock signal fr. Thereafter, the clock period of the feedback clock signal fd starting from the rising edge edge4 is set to xcfx841 which is longer than the clock period of the input clock signal fr while the clock period of the feedback clock signal fd starting from the rising edge edge5 is set to xcfx842 in the same manner.
Also, as illustrated in FIG. 3, if the multiplication factor of the input clock signal fr is M, the period xcfx841 and the period xcfx842 are calculated as
xcfx841=[(d+xcex94d)xc3x972+dxc3x972]xc3x972xc3x97M 
xcfx842=[(d+xcex94d)xc3x971+dxc3x973]xc3x972xc3x97M.
and therefore the difference between the period xcfx841 and the period xcfx842 is calculated as
xcfx841xe2x88x92xcfx842=Mxc3x97xcex94dxc3x972.
The difference between the period xcfx841 and the period xcfx842 ensues jittering of the feedback clock signal fd and, understood from the above described equations, the amount of jittering becomes large as the multiplication factor M becomes large so that it can be the case that the specification of the system can not be satisfied.
FIG. 4 is a timing chart showing the relationship among the feedback clock signal fd, the output clock signal fo, the signal dlysw2 and the input clock signal fr as described above, in which FIG. 4(a) is a graphic diagram showing the feedback clock signal fd with the clock period of xcfx841; FIG. 4(b) is a graphic diagram showing the feedback clock signal fd with the clock period of xcfx842; and FIG. 4(c) is a graphic diagram showing the input clock signal fr. As illustrated in FIG. 4, while the clock period of the feedback clock signal fd switches between the period xcfx841 and the period xcfx842, the output clock signal fo has the jitter of (xcex94dxc3x972) while the feedback clock signal fd has the jitter of (Mxc3x97xcex94dxc3x972).
FIG. 5 is a graphic diagram showing the relationship between the jitter of the feedback clock signal fd and the jitter of the variable delay xcex94d with reference to the multiplication factor M in the case where the output frequency of the output clock signal fo is fixed to a desired value. In the figure, when a higher frequency output clock signals is desired, it is understood that the variable delay xcex94d has to be set to a smaller value in order to suppress the jitter of the feedback clock signal fd.
In contrast with this, with the recent advent of high speed semiconductor devices and therefore the increase in the clock frequency as required in the system for keeping pase therewith, a higher multiplication factor is increasingly required of the multiplied clock generating circuit. Because of this, it is difficult to generate an output clock with a higher multiplication factor simply by controlling the variable delay xcex94d as illustrated in FIG. 5.
In the case where the output clock signal fo is generated by multiplying the input clock signal fr by the multiplication factor M (M is an arbitrary integer) and divided by M in order to generate the feedback clock signal fd, which is always controlled to match the input clock signal fr as described above, the clock period of the feedback clock signal fd is controlled in order to switch between the period xcfx841 corresponding to a frequency lower than that of the input clock signal fr and the period xcfx842 corresponding to a frequency higher than that of the input clock signal fr. Because of this, the jitter of the feedback clock signal fd is proportional to the multiplication factor M so that it becomes difficult to suppress the jitter of the feedback clock signal fd when a higher frequency output clock signals as multiplied by a larger multiplication factor M is needed.
An aspect of the present invention provides a multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M, said multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing said output clock signal by a factor M; a phase comparator circuit which is configured to receive said input clock signal and said feedback clock signal as generated by said frequency divider circuit, to compare the phase of said input clock signal with the phase of said feedback clock signal and to output a phase displacement signal indicative of the phase relationship between said input clock signal and said feedback clock signal; a comparator which is configured to receive said phase displacement signal, to count said output clock signal within each cycle of said feedback clock signal while said phase displacement signal is indicative that there is a phase displacement between said feedback clock signal and said input clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, and to output a delay time adjustment signal on the basis of the result of the comparison; and an oscillator circuit which is capable of controlling said output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of said delay time adjustment signal and outputting said output clock signal as controlled.
Another aspect of the present invention provides a multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M, said multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing said output clock signal by a factor M; a phase comparator circuit which is configured to receive said input clock signal and said feedback clock signal as generated by said frequency divider circuit, to compare the phase of said input clock signal with the phase of said feedback clock signal and to output a phase displacement signal indicative of the phase relationship between said input clock signal and said feedback clock signal; a phase control circuit which is configured to receive said phase displacement signal, to count said output clock signal within each cycle of said feedback clock signal while said phase displacement signal is indicative that there is a phase displacement between said feedback clock signal and said input clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, and to output a phase adjustment signal on the basis of the result of the comparison in the case where the same count of said feedback clock signal is maintained for a predetermined number of cycles; and an oscillator circuit which is configured to receive said phase adjustment signal from said phase control circuit as a delay time adjustment signal and is capable of controlling said output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of said delay time adjustment signal and outputting said output clock signal as controlled.
A further aspect of the present invention provides a multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M, said multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing said output clock signal by a factor M; a phase comparator circuit which is configured to receive said input clock signal and said feedback clock signal as generated by said frequency divider circuit, to compare the phase of said input clock signal with the phase of said feedback clock signal and to output a signal indicative of the phase relationship between said input clock signal and said feedback clock signal; a register circuit which is configured to latch the output signal of said phase comparator circuit and to output, as a phase displacement signal, said output signal of said phase comparator circuit as latched in synchronism with said output clock signal; a phase control circuit which is configured to receive said phase displacement signal outputted from said register circuit, to count said output clock signal in relation to said phase displacement signal outputted from said register circuit within each cycle of said feedback clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, and to output a phase adjustment signal on the basis of the result of the comparison in the case where the same count of said feedback clock signal is maintained for a predetermined number of cycles; and a comparator which is configured to receive said phase displacement signal outputted from said register circuit, to count said output clock signal in relation to said phase displacement signal outputted from said register circuit within each cycle of said feedback clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, to output a delay time adjustment signal with reference to the result of the comparison if the phase adjustment signal is not given from said phase control circuit and to output a delay time adjustment signal when the number as counted of said feedback clock signal of each cycle of said feedback clock signal reaches the number as counted of said feedback clock signal in the cycle previous to said each cycle decremented by 1 if the phase adjustment signal is given from said phase control circuit; an oscillator circuit which is capable of controlling said output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of said delay time adjustment signal and outputting said output clock signal as controlled; and an oscillator control circuit which is configured to count said output clock signal in relation to said phase displacement signal outputted from said register circuit and the output signal of said comparator, to output said delay time adjustment signal to said oscillator circuit in order to shorten the clock period of said feedback clock signal by a value corresponding to the number as counted by said oscillator control circuit and said predetermined delay time or in order to elongate the clock period of said feedback clock signal by a value corresponding to the number as counted by said oscillator control circuit.
A still further aspect of the present invention provides a multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M, said multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing said output clock signal by a factor M; a phase comparator circuit which is configured to receive said input clock signal and said feedback clock signal as generated by said frequency divider circuit, to compare the phase of said input clock signal with the phase of said feedback clock signal and to output a signal indicative of the phase relationship between said input clock signal and said feedback clock signal; a register circuit which is configured to latch the output signal of said phase comparator circuit and to output, as a phase displacement signal, said output signal of said phase comparator circuit as latched in synchronism with said output clock signal; a frequency control circuit which is configured to receive said phase displacement signal outputted from said register circuit, said input clock signal and said feedback clock signal and to output first and second frequency control signals indicative of a predetermined width by which the clock period of said feedback clock signal is adjusted if the clock period of said feedback clock signal is longer than the clock period of said input clock signal by no smaller than a predetermined width; a comparator which is configured to receive said phase displacement signal outputted from said register circuit, to count said output clock signal in relation to said phase displacement signal outputted from said register circuit within each cycle of said feedback clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, and to output a delay time adjustment signal on the basis of the result of the comparison or the number as counted and said phase displacement signal outputted from said register circuit; an oscillator circuit which is capable of controlling said output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of said delay time adjustment signal and outputting said output clock signal as controlled; and an oscillator control circuit which is configured to count said output clock signal in relation to said phase displacement signal outputted from said register circuit and the output signal of said comparator, to output said delay time adjustment signal to said oscillator circuit in order to shorten the clock period of said feedback clock signal by a value corresponding to the number as counted by said oscillator control circuit and said predetermined delay time or in order to elongate the clock period of said feedback clock signal by a value corresponding to the number as counted by said oscillator control circuit and said predetermined delay time if said first control signal is given from said frequency control circuit, and in order to shorten the clock period of said feedback clock signal on the basis of said second the control signal as given from said frequency control circuit.
A still further aspect of the present invention provides a multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M, said multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing said output clock signal by a factor M; a phase comparator circuit which is configured to receive said input clock signal and said feedback clock signal as generated by said frequency divider circuit, to compare the phase of said input clock signal with the phase of said feedback clock signal and to output a signal indicative of the phase relationship between said input clock signal and said feedback clock signal; a register circuit which is configured to latch the output signal of said phase comparator circuit and to output, as a phase displacement signal, said output signal of said phase comparator circuit as latched in synchronism with said output clock signal; a phase control circuit which is configured to receive said phase displacement signal outputted from said register circuit, to count said output clock signal in relation to said phase displacement signal outputted from said register circuit within each cycle of said feedback clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, and to output a phase adjustment signal on the basis of the result of the comparison in the case where the same count of said feedback clock signal is maintained for a predetermined number of cycles; and a frequency control circuit which is configured to receive said phase displacement signal outputted from said register circuit, said input clock signal and said feedback clock signal and to output a frequency control signal if the clock period of said feedback clock signal is longer than the clock period of said input clock signal by no smaller than a predetermined width; a comparator which is configured to receive said phase displacement signal outputted from said register circuit, to count said output clock signal in relation to said phase displacement signal outputted from said register circuit within each cycle of said feedback clock signal, to compare the numbers as counted in successive cycles of said feedback clock signal, to output a delay time adjustment signal on the basis of the result of the comparison, and to maintain an initialized state thereof when a first control signal is given from said frequency control circuit; and an oscillator circuit which is capable of controlling said output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of said delay time adjustment signal and outputting said output clock signal as controlled; and an oscillator control circuit which is configured to count said output clock signal in relation to said phase displacement signal outputted from said register circuit and the output signal of said comparator, to output said delay time adjustment signal to said oscillator circuit in order to shorten the clock period of said feedback clock signal by a value corresponding to the number as counted by said oscillator control circuit and said predetermined delay time or in order to elongate the clock period of said feedback clock signal by a value corresponding to the number as counted by said oscillator control circuit and said predetermined delay time if said first control signal is given from said frequency control circuit, and in order to shorten the clock period of said feedback clock signal on the basis of said second the control signal as given from said frequency control circuit.